抑制單級PFC中儲能電容電壓的拓撲研究

摘要：抑制儲能電容電壓是單級功率因數校正要解決的主要問題，儲能電容電壓隨輸入電壓和負載的變化而變化，在輸入高壓或輕載時，電容電壓可能達到上千伏，而且變換器的效率低。介紹了幾種改進的拓撲結構來降低電容電壓，分別討論了其優缺點。通過對現有拓撲的分析，得出了一種新型拓撲結構。 敘詞：功率因數校正 單級 拓撲 Abstract：It is very important for single-stage power factor correction to suppress the energy-stored capacitor voltage, which varies with the input voltage and load, capacitor voltage is likely to amount to 1000 volt at the high input voltage or light load.；Converters have low efficiency. Several improved topologies are introduced to decrease the capacitor voltage, the merits and limitations of them are analyzed respectively. An novel topology is got by analyzing present topologies. Keyword：power factor correction (PFC) single stage topology